INTERNATIONAL CONFERENCES

33. Sang-Yun Nam, Hyeonho Park, Won-Gyu Kim, and Sung-Wan Hong, "A 0.087 fs FOM Current-mirror-based Analog-assisted Digital LDO with VO Ripple Optimization," in IEEE Symp. VLSI Circuits (VLSI), Accepted.
32. Joo-Mi Cho, Hyeon-Ji Choi, Hyo-Jin Park, Jaeho Han, Kwang-Seok Yun, Jong-Pil Im, and Sung-Wan Hong, "2,771% Power Improvement Triple-source Ground-symmetric Pile-up Resonant Energy Harvester," in IEEE Symp. VLSI Circuits (VLSI), Accepted.
31. Hyun-Woo Jeong, Chan-Ho Lee, Sang-Yun Nam, and Sung-Wan Hong, " A Gm-Boosted 3-stage Amplifier with Gain-Enhancing Feedforward Path for CL of 40-160nF," in IEEE Symp. VLSI Circuits (VLSI), Accepted.
30. Jeong-Hun Kim, Young-Jun Jeon, Won-Gyu Kim, Jaeseung Lee, Jun-Hyeok Yang, and Sung-Wan Hong, "A 2A Fully Analog Distribution LDO with Noise Immunity for a SoC," in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2025.
29. Young-Jun Jeon, Jeong-Hun Kim, Won-Gyu Kim, and Sung-Wan Hong, "A Sub-1V, 50mV Dropout LDO using Pseudo-Impedance Buffer with Phase-Margin Improvement Design," in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2025.
28. Hyeon-Ji Choi, Chan-Ho Lee, Young-Jun Jeon, Hyeonho Park, Jeong-Hun Kim, Young-Jin Woo, Ju-Pyo Hong, Haifeng Jin, Sung-Wan Hong, "A 92.7% Peak Efficiency 12V-to-60V Input to 1.2V Output Hybrid DC-DC Converter based on a Series-Parallel-Connected Switched Capacitor," in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024.
27. Hyo-Jin Park, Joo-Mi Cho, Chan-Ho Lee, Young-Ju Oh, Hyunwoo Jeong, Jun-Hyeok Yang, Jaeseung Lee, and Sung-Wan Hong, "A 97.18% Peak-Efficiency Asymmetrically Implemented Dual-phase (AID) Converter with a full Voltage-Conversion Ratio (VCR) between 0-and-1," in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024.
26. Ho-Chan Ahn, Joo-Mi Cho, Hyeon-Ji Choi, Chan-Ho Lee, Chan-Kyu Lee, and Sung-Wan Hong, "A 2 A Maximum Load Current Capable 0-to-1 μF Off-chip Capacitor N-type LDO using Dual Dynamic Negative Feedback Loop and an Improved Error Amplifier," in IEEE European Solid-State Circuits Conference (ESSCIRC), Sep. 2023.
25. Hyo-Jin Park, Joo-Mi Cho, Hyeon-Ji Choi, Chan-Ho Lee, and Sung-Wan Hong, "96.48% Peak-Efficiency Continuous-Current Step-Up Battery Charger (CC-SUBC) with Dual Energy-Harvesting Sources for Automotive Application," in IEEE Symp. VLSI Circuits (VLSI), Jun. 2023.
24. Chan-Ho Lee, Hyo-Jin Park, Joo-Mi Choi, Hyeon-Ji Choi, Young-Jun Jeon, and Sung-Wan Hong, "A 1V 20.7uW Four-Stage Amplifier Capable of Driving a 4-to-12nF Capacitive Load with 1.07MHz GBW with an Improved Active Zero," in IEEE Symp. VLSI Circuits (VLSI), Jun. 2023.
23. Young-Ju Oh, Hyo-Jin Park, Joo-Mi Cho, Hyeon-Ji Choi, Su-Min Park, Chan-Ho Lee, Esun Baik, Chan-Kyu Lee, Ho-Chan Lee, and Sung-Wan Hong, "A High Slew-rate Wide-range Capacitive Load Driving Buffer Amplifier with Correlated Dual Positive Feedback Loops," in IEEE International SoC Design Conference (ISOCC), Oct. 2022.
22. Hyeon-Ji Choi, Joo-Mi Cho, Hyo-Jin Park, and Sung-Wan Hong, "An Output Capacitor-less Low-dropout Regulator using a Wide-range Single-Stage Gain-Boosted Error Amplifier and a Frequency-dependent Buffer with a Total Compensation Capacitance of 2.5 pF in 0.5 um CMOS," in IEEE Asian Solid-State Circuits conference (ASSCC), Nov. 2021.
21. Hyo-Jin Park, Joo-Mi Cho, Hyunji Choi, Esun Baik, Jeeyoung Shin, and Sung-Wan Hong, "A 18 uA Rail-to-Rail Class-AB Operational Amplifier with a High-Slew Miller Compensation (HSMC) Technique with 240% Settling Time Reduction in 0.18 um," in IEEE European Solid-State Circuits conference (ESSCIRC), Sep. 2021.
20. Joo-Mi Cho, Hyo-Jin Park, Hyunji Choi, Esun Baik, Jeeyoung Shin, and Sung-Wan Hong, "A 100-MHz 81.2% All-Paths Inductor-Connected Buck-Converter with Balanced Conduction-Losses and Continuous Path-Currents," in IEEE European Solid-State Circuits conference (ESSCIRC), Sep. 2021.
19. Joo-Mi Cho, Hyo-Jin Park, and Sung-Wan Hong, "A 0.93-uW Single-Stage Rail-to-Rail Class AB Buffer Amplifier Improving DC gain and Slew-Rate with Different-Ratio Current-Mirrors and Positive-Feedback Loops," in IEEE Symp. VLSI Circuits (VLSI), Jun. 2021.
18. Sung-Wan Hong, “A 13.56 MHz Current-Mode Wireless Power and Data Receiver with Efficient Power Extracting Controller and Energy Shift Keying Technique for Loosely Coupled Implantable Devices,” in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020, pp. 486 - 488.

17. Sung-Wan Hong, “A 1.46 mm2 Simultaneous Energy Transferring Single-Inductor Bipolar-Output (SETSIBO) with a Flying Capacitor for High Efficient AMOLED Display in 0.5 μm CMOS,” in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020, pp. 200 - 202.

16. Sung-Won Choi, Yeunhee Huh, Sang-Hui Park, Kye-Seok Yoon, Jun-Suk Bang, Se-Un Shin, Yong-Min Ju, Yujin Yang, Junghyuk Yoon, Changyong Ahn, Taekseoung Kim, Sung-Wan Hong, and Gyu-Hyoeng Cho, “A Quasi-Digital Ultra-Fast Capacitor-Less Low-Dropout Regulator Based on Comparator Control for x8 Current Spike of PCRAM Systems,” in IEEE Symp. VLSI Circuits (VLSI), Jun. 2018, pp. 107 – 108.

15. Yeunhee Huh, Se-Un Shin, Sung-Wan Hong, Young-Jin Woo, Yong-Min Ju, Sung-Won Choi, and Gyu-Hyeong Cho, “A Hybrid Dual-Path Step-Down Converter with 96.2 % Peak Efficiency Using a 250mΩ Large-DCR Inductor,” in IEEE Symp. VLSI Circuits (VLSI), Jun. 2018, pp. 225 – 226.

​14. Se-Un Shin, Yeunhee Huh, Yongmin Ju, Sungwon Choi, Changsik Shin, Young-Jin Woo, Minseong Choi, Se-Hong Park, Young-Hoon Sohn, Min-Woo Ko, Youngsin Jo, Hyunki Han, Hyung-Min Lee, Sung-Wan Hong, Wanquan Qu, and Gyu-Hyeong Cho, “A 95.2% efficiency dual-path DC-DC step-up converter with continuous outputs current delivery and low voltage ripple", in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2018, pp. 430 - 432.

​13. Kye-Seok Yoon, Sung-Wan Hong, Jun-Suk Bang, Sang-Han Lee, Sung-Won Choi, and Gyu-Hyeong Cho, “A 1452-% power extraction improvement energy harvesting circuit with simultaneous energy extraction from a piezoelectric transducer and a thermoelectric generator”, in IEEE Symp. VLSI Circuits (VLSI), Jun. 2017, pp. 202 – 203.

​12. Yeunhee Huh, Sung-Wan Hong, Sang-Hui Park, Jun-Suk Bang, Changbyung Park, Sungsoo Park, Hui-Dong Gwon, Se-Un Shin, Hongsuk Shin, Yong-Min Ju, Ji-Hun Lee, and Gyu-Hyeong Cho, “A 10.1" 56-channel, 183 uW/electrode, 0.73 mm2/sensor high SNR 3D hover sensor based on enhanced signal refining and fine error calibrating techniques”, in IEEE Symp. VLSI Circuits (VLSI), Jun. 2017, pp. 308 – 309.

​11. Sung-Wan Hong, and Gyu-Hyeong Cho, “7.4μW Ultra-high slew-rate pseudo single-stage amplifier driving 0.1-to-15nF capacitive load with >69° phase margin”, in IEEE Symp. VLSI Circuits (VLSI), Jun. 2015, pp. 296 – 297.

​10. Si-Duk Sung, Sung-Wan Hong, Jun-Suk Bang, Ji-Seon Peak, Seung-Chul Lee, T. B. H. Cho, and Gyu-Hyeong Cho, “86.55% Peak efficiency envelope modulator for 1.5W 10MHz LTE PA without AC coupling capacitor, in IEEE Symp. VLSI Circuits (VLSI), Jun. 2015, pp. 342 – 343.

​9. Sang-Han Lee, Jun-Suk Bang, Kye-Suk Yoon, Sung-Wan Hong, Chang-Sik Shin, Min-Yong Jung, and Gyu-Hyeong Cho, “A 0.518mm2 quasi-current-mode hysteretic buck DC-DC converter with 3μs load transient response in 0.35μm BCDMOS,” in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2015, pp. 1 – 3.

​8. Sung-Wan Hong, and Gyu-Hyeong Cho, “Inverting buck-boost DC-DC converter for mobile AMOLED display with real-time self-tuned minimum power-loss tracking scheme,” in IEEE Custom Integrated Circuits Conference (CICC), Sep. 2014, pp. 1 – 4.

​7. Young-Sub Yuk, Seungchul Jung, Hui-Dong Gwon, Sukhwan Choi, Si-Duk Sung, Tae-Hwang Kong, Sung-Wan Hong, Jun-Han Choi, Min-Yong Jeong, Jong-Pil Im, Seung-Tak Ryu, and Gyu-Hyeong Cho, “An energy pile-up resonance circuit extracting maximum 422% energy from piezoelectric material in a dual-source energy-harvesting interface,” in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2014, pp. 402 – 403.

​6. Sung-Wan Hong, Seungchul Jung, Changbyung Park, Tae-Hwang Kong, Min-Yong Jung, Seung-Tak Ryu, and Gyu-Hyeong Cho, “High-gain wide-bandwidth capacitor-less low-dropout regulator with zero insertion utilizing frequency response of inner loops,” in IEEE Symp. VLSI Circuits (VLSI), Jun. 2013, pp. 168 – 169.

​5. Tae-Hwang Kong, Sung-Wan Hong, Sungwoo Lee, Jong-Pil Im, and Gyu-Hyeong Cho, “A 0.791mm2 fully on-chip controller with self-error-correction for boost DC-DC converter based on Zero-Order Control,” in IEEE Custom Integrated Circuits Conference (CICC), Sep. 2012, pp. 1 – 4.

​4. Sung-Wan Hong, Tae-Hwang Kong, Seungchul Jung, Sungwoo Lee, Se-Won Wang, Jong-Pil Im, and Gyu-Hyeong Cho, “High area-efficient DC-DC converter using Time-Mode Miller Compensation (TMMC),” in IEEE Symp. VLSI Circuits (VLSI), Jun. 2012, pp. 180 – 181.

​3. Jong-Pil Im, Se-Won Wang, Kang-Ho Lee, Young-Jin Woo, Young-Sub Yuk, Tae-Hwang Kong, Sung-Wan Hong, Seung-Tak Ryu, and Gyu-Hyeong Cho, “A 40mV transformer-reuse self-startup boost converter with MPPT control for thermoelectric energy harvesting,” in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2012, pp. 104 – 106.

​2. Tae-Hwang Kong, Young-Jin Woo, Se-Won Wang, Sung-Wan Hong, and Gyu-Hyeong Cho, “Zero-order control of boost DC-DC converter with transient enhancement using residual current,” in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2011, pp. 390 – 392.

​1. Se-Won Wang, Hanh-Phuc Le, Young-Jin Woo, Young-Sub Yuk, Jin-Huh, Tae-Hwang Kong, Jong-Pil Im, Byung-Sang Jung, Jun-Han Choi, Sung-Wan Hong, and Gyu-Hyeong Cho, “Low-Power Consumptive Luminance Compensation for a Digital Driving AMOLED Display using a Multiple Output Boost Converter,” in SID Symposium Digest of Technical Papers, Volume 41, Issue 1, May 2010, pp. 898–901.

DOMESTIC CONFERENCES